M12L128324A_1 Datasheet, PDF (33/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
Operation temperature condition -40°C~85°C
Note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA1
0
0
1
1
BA0
0
1
0
1
Active & Read/Write
Bank A
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
0
1
BA1
0
0
1
1
0
0
1
1
BA0
0
1
0
1
0
1
0
1
Operating
Disable auto precharge, leave A bank active at end of burst.
Disable auto precharge, leave B bank active at end of burst.
Disable auto precharge, leave C bank active at end of burst.
Disable auto precharge, leave D bank active at end of burst.
Enable auto precharge , precharge bank A at end of burst.
Enable auto precharge , precharge bank B at end of burst.
Enable auto precharge , precharge bank C at end of burst.
Enable auto precharge , precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
0
0
0
0
1
BA1
0
0
1
1
X
BA0
0
1
0
1
X
Precharge
Bank A
Bank B
Bank C
Bank D
All Banks
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
33/49