M12L128324A_1 Datasheet, PDF (19/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
Operation temperature condition -40°C~85°C
Self refresh entry command
( CS , RAS , CAS , CKE = Low , WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the M12L128324A exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
Burst stop command
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 8 Burst stop command
No operation
( CS = Low , RAS , CAS , WE = High)
This command is not a execution command. No operations begin or terminate by
this command.
CLK
CKE
H
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 9 No operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
19/49