M12L128324A_1 Datasheet, PDF (37/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
Operation temperature condition -40°C~85°C
Page Read Cycle at Different Bank @ Burst Length = 4
CLOCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18 19
CKE
CS
*Note1
HIGH
RAS
CAS
*Note2
ADDR
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BA1
BA0
A10/AP
CL=2
DQ
CL=3
RAa
RBb
WE
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 _QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQM
Row Active
( A-Bank)
Read
(A -Ba nk )
Read
(B -Ba nk )
Row Active
( B-B ank )
Row Active
(C-Ban k)
Read
( C- Ba nk )
Row Active
( D- Bank )
Read
( D- Ba nk )
Pr e c har g e
(D -B an k)
Pr e char g e
(C -B an k)
Pr e c har g e
(A- Ban k)
Pr e c har g e
(B- Ban k)
:Don't Care
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
37/49