M12L128324A_1 Datasheet, PDF (39/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
Operation temperature condition -40°C~85°C
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 _{15 16}
17 ¹⁸ 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
BA1
CAa
RDb
CDb RBc
CBc
BA0
A10/AP
CL =2
DQ
CL =3
RAa
tRCD
*Note2
RBb
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
RAc
t *Note1
CDL
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1 QBc2
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
W rite
(D-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
:Don't Care
*Note : 1. tCDL should be met to complete write.
2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
39/49