M12L128324A_1 Datasheet, PDF (26/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
8. Burst Stop & Interrupted by Precharge
M12L128324A
Operation temperature condition -40°C~85°C
CLK
1)W rite Burst Stop (BL=8)
CMD
WR
STOP
DQM
DQ
D0
D1
D2
D3
D4
D5
tB DL ^*Note2
CLK
1)W rite in terru pted b y p rech arg e (B L= 4 )
CMD
DQM
WR
tRDL
PRE
*N ote 1
DQ
D0 D1 D2 Mask
CLK
2)Read Burst Stop (BL=4)
CMD
RD
DQ(CL2)
STO P
Q0
*Note3
Q1
DQ(CL3)
Q0 Q1
CLK
2)Read interrup ted b y p recharg e (BL=4)
CMD
RD
PR E ^*Note3
DQ(CL3)
DQ(CL2)
Q0 Q1
Q0 Q1
9. MRS
1)Mod e Reg ister Set
CLK
CMD
*Note4
PRE
tRP
MRS
ACT
2CLK
*Note: 1. tRDL : 2 CLK; Last data in to Row Precharge.
2. tBDL : 1 CLK ; Last data in to burst stop delay.
3. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
4. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
26/49