M12L128324A_1 Datasheet, PDF (30/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
Operation temperature condition -40°C~85°C
Current
State
CS RAS CAS WE
BA
HXXX
X
L HHH
X
Precharging L H H L
X
LHLX
BA
L LHH
BA
L LHL
BA
L
L
L
X
X
HXXX
X
L HHH
X
Row
L HH L
X
Activating L H L X
BA
L LHH
BA
L LHL
BA
L
L
L
X
X
HXXX
X
L HHX
X
Refreshing L H L X
X
L LHX
X
L
L
L
X
X
HXXX
X
Mode
L HHH
X
Register
L
HH
L
X
Accessing L H L X
X
L LXX
X
ADDR
X
X
X
CA
RA
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
ACTION
NOP Idle after tRP
NOP Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP Idle after tRDL
ILLEGAL
NOP Row Active after tRCD
NOP Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP Idle after tRC
NOP Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP Idle after 2clocks
NOP Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
Note
2
2
2
4
2
2
2
2
Abbreviations :
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note :
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
30/49