M12L128324A_1 Datasheet, PDF (10/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128324A
Operation temperature condition -40°C~85°C
SIMPLIFIED TRUTH TABLE
Register
Refresh
COMMAND
Mode Register set
Auto Refresh
Self
Refresh
Entry
Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A9~A0
H
X LL L L X
OP CODE
H
H
LL L H X
X
L
LH H H X
L
H
X
HX X X X
Note
1,2
3
3
3
3
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
H
Column Address Auto Precharge Enable
Write &
Auto Precharge Disable
H
Column Address Auto Precharge Enable
Burst Stop
H
X LL H H X
V
X LH L H X
V
X LH L L X
V
X LH H L X
Row Address
L Column 4
Address
H _(A0~A7) 4,5
L Column 4
Address
H _(A0~A7) 4,5
X
6
Precharge
Bank Selection
All Banks
V
L
H
X LL H L X
X
X
H
HX X X
Clock Suspend or
Entry
H
L
X
Active Power Down
LV V V
X
Exit
L
H XX X X X
HX X X
Entry
H
L
X
Precharge Power Down Mode
LH H H
X
HX X X
Exit
L
H
X
LV V V
DQM
No Operating Command
H
X
V
X
7
HX X X
H
X
X
X
LH H H
Note :
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
1.OP Code : Operating Code
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
10/49