M12L128168A_06 Datasheet, PDF (40/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128168A
Self Refresh Entry & Exit Cycle
0
1
2
3
4
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7
8
9
10
11 12 13
14 15 16 17 18 19
CLOCK
CKE
*Note2
*Note1
*Note3
*Note4
tRFCmin
*Note6
tSS
CS
*Note5
RAS
CAS
*Note7
ADDR
A13,A12
A10/AP
DQ
Hi-Z
Hi-Z
WE
DQM
Self Refresh Entry
Self Ref resh Exit
Auto Refresh
: Don't care
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t_RAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t_RFC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
40/43