M12L128168A_06 Datasheet, PDF (35/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Read & Write cycle with Auto Precharge @ Burst Length = 4
M12L128168A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
Ra
Rb Ca
Cb
A13
A12
A10/AP
Ra
CL =2
DQ
CL =3
Rb
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
WE
DQM
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Row Active
( D - Bank )
Auto Precharge
Start Point
Write with
Auto Precharge
( D- Ban k)
Auto Precharge
Start Point
( D- Ban k)
:Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
35/43