M12L128168A_06 Datasheet, PDF (30/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128168A
Read & Write Cycle at Same Bank @ Burst Length = 4
CLOCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18
19
CKE
CS
RAS
CAS
tRCD
t *Note1
RC
HIGH
*Note2
ADDR
Ra
Ca
Rb
Cb
A13
A12
A10/AP
Ra
CL=2
DQ
CL=3
WE
Rb
tOH
Qa0 Qa1 Qa2
tSAC
tOH
Qa0 Qa1
tSAC
Qa3
tS HZ *Note3
Qa2
Qa3
tS HZ *Note3
`
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
tRDL
DQM
Row Active
(A-Bank)
Read
(A- Ban k)
Precharge
( A- Ban k)
Row Active
( A- Ban k)
Write
( A- Ban k)
Precharge
(A- Ban k)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (t_SHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
30/43