M12L128168A_06 Datasheet, PDF (13/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
COMMANDS
Mode register set command
( CS , RAS , CAS , WE = Low)
The M12L128168A has a mode register that defines how the device operates. In
this command, A0 through A13 are the data input pins. After power on, the mode
register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L128168A cannot accept any
other commands.
Activate command
( CS , RAS = Low, CAS , WE = High)
The M12L128168A has four banks, each with 4,096 rows.
This command activates the bank selected by A12 and A13 (BS) and a row
address selected by A0 through A11.
This command corresponds to a conventional DRAM’s RAS falling.
M12L128168A
CLK
CKE
H
CS
RAS
CAS
WE
A12, A13
A10
Add
Fig. 1 Mode register set
command
CLK
CKE
H
CS
RAS
CAS
WE
A12, A13
(Bank select)
A10
Add
Row
Row
Fig. 2 Row address strobe and
bank active command
Precharge command
( CS , RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by A12 and A13
(BS). When A10 is High, all banks are precharged, regardless of A12 and A13. When
A10 is Low, only the bank selected by A12 and A13 is precharged.
After this command, the M12L128168A can’t accept the activate command to the
precharging bank during t_RP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
Elite Semiconductor Memory Technology Inc.
CLK
CKE
H
CS
RAS
CAS
WE
A12, A13
(Bank select)
A10
(Precharge select)
Add
Fig. 3 Precharge command
Publication Date: Oct. 2006
Revision: 2.0
13/43