M12L128168A_06 Datasheet, PDF (32/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Page Read Cycle at Different Bank @ Burst Length = 4
M12L128168A
CLOCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18 19
CKE
CS
*Note1
HIGH
RAS
CAS
*Note2
ADDR
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
A13
A12
A10/AP
CL=2
DQ
CL=3
RAa
RBb
WE
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 _QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQM
Row Active
( A-Bank)
Read
(A -Ba nk )
Read
(B -Ba nk )
Row Active
( B-B ank )
Row Active
(C -B an k)
Read
( C- Ba nk )
Row Active
( D- Ba nk )
Read
( D- Ba nk )
Precharge
(D -B an k)
Precharge
(C-Ban k)
Precharge
(A- Bank)
Precharge
(B- Bank)
:Don't Care
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
32/43