M12L128168A_06 Datasheet, PDF (34/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128168A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15 16
17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
A13
CAa
RDb
CDb RBc
CBc
A12
A10/AP
RAa
CL =2
DQ
CL =3
RBb
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
RAc
t *Note1
CDL
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1 QBc2
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1
WE
DQM
Row Active Read
(A-Bank) (A-Bank)
Precharge
( A- B an k )
Row Active
(D-Bank)
W rite
(D-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
:Don't Care
*Note : 1. t_CDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
34/43