M12L128168A_06 Datasheet, PDF (27/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128168A
Single Bit Read-Write-Read Cycle(Same Page) @ CAS Latency = 3,Burst Length = 1
CLOCK
CKE
CS
RAS
CAS
ADDR
A13,A12
tCH
0
1
2
3
4
5
6
tCC
*Note1
tCL
tRAS
tRC
tSH
tRCD
7
8
9
10
11
12 13
14
15
16 17
18 19
HIGH
tS
H
tSS
tRP
tSS
tSH
tCCD
tSH
Ra
tSS
*Note2
BS
tSS
Ca
*No te 2, 3
BS
Cb
Cc
*Note2,3
BS
*No te 2, 3
BS
*Note4
BS
Rb
*Note2
BS
A10/AP
Ra
DQ
WE
DQM
*Note3
*Note3
*Note3
*Note4
Rb
tSH
tSAC
Qa
Db
Qc
tSLZ
tSS
tOH
tSH
tSS
tSS
tSH
Row Active
Read
Write
Read
Row Active
Precharge
:Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
27/43