M12L128168A_06 Datasheet, PDF (1/43 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
SDRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
M12L128168A
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE COMMENTS
M12L128168A-5TG 200MHz TSOP II
Pb-free
M12L128168A-6TG 166MHz TSOP II
Pb-free
M12L128168A-7TG 143MHz TSOP II
Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VS SQ 12
DQ7 13
VDD 14
LDQM 15
WE 16
CAS 17
RAS 18
CS 19
A13 20
A12 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 N C
39 UDQM
38 CLK
37 CKE
36 N C
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
1/43