S1X60000 Datasheet, PDF (266/358 Pages) Epson Company – EMBEDDED ARRAY

Chapter 10 Circuit Design that Takes Testability into Account
• ATPG enable input pin (ATPGEN) [Dedicated pin]
This external input pin activates ATPG run mode. If any design exists that requires
that the state be fixed, or for the outputs of blocks (including those that become
black boxes during simulation), functional macros, and RAM cells for which the
internal logic becomes unstable, this pin must be used to fix (determine) the values.
Unless this procedure is used, the fault detection rate decreases considerably.
Prepare this external input pin as a dedicated pin.
b. Clock design
For the circuit to be scanned, clock design is very important. If the clock design is
complicated, not only is the fault detection rate reduced, but the generated test pattern
also becomes unstable. In such a case, the intended purposes of scan and ATPG cannot
be achieved. Therefore, we basically recommend synchronized design. Follow the rules
described below in the design of a clock.
Keep in mind, as well, that the clock lines require optimization by CTS (Clock Tree
Synthesis). For details, refer to Section 9.3, “Clock Tree Synthesis.”
• Directly controllable structure from the outside [Essential]
The scan clock must propagate from an external input pin to the internal registers
without being distorted in the clock waveform. Although it does not matter whether
an internally generated clock is present during normal operation, there must
logically be no internally generated clocks in ATPG run mode. Examples are shown
in Figures 10-17 through 10-20.
§ Ideal clock
Shown in Figure 10-17 is an example of an ideal clock design. If the circuit is
designed from the beginning in such a way that the clock for all registers is supplied
from an external input pin as in this case, processing the clock lines by CTS makes it
unnecessary to correct them for purposes of scan design. Because clock line
corrections affect the timing of the entire circuit, it is important to take scan design
into consideration from the beginning of your design work.
clock
Figure 10-17 Ideal Clock
§ Processing of internally generated clocks 1
If an internally generated clock is used, insert a circuit that bypasses the clock
generating part (see Figure 10-18) and employ a design that applies CTS processing
to ATPG run mode. However, employment of this processing requires caution, as
MUX cells are added to the clock lines in that processing, which may make it
difficult to adjust the timing with the clocks used for other circuit blocks.
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