S1X60000 Datasheet, PDF (128/358 Pages) Epson Company – EMBEDDED ARRAY

Chapter 6 Memory Blocks
6.2.5 Functional Description
6.2.5.1 1 port RAM (Clock Synchronous Type)
(1) Input/output signals and block diagram
Table 6-21 Signal Description of a 1 port RAM (Clock Synchronous Type)
Input/output signal
Symbol
Name
CK
Clock input
XCS
Chip select
XWE
A0 to An
D0 to Dn
Write enable
Address input
Data input
Y0 to Yn Data output
Description
The rising edge (L(H) on the clock input (CK) latches chip select
(XCS), write enable (XWE), address inputs (A0 to An), and data
inputs (D0 to Dn) into the internal logic of the RAM.
Latched by the rising edge on the clock input (CK). When XCS is
latched Low, chip select is enabled.
Latched by the rising edge on the clock input (CK). When XWE is
latched Low, write is enabled; when High, read is enabled.
Latched by the rising edge on the clock input (CK).
Latched by the rising edge on the clock input (CK). The data is written
into memory cells when write enable (XWE) = Low.
During readout, the data from memory cells are output after a
specified access time has elapsed from the rising edge on the clock
input (CK). During write, the write data is output from these pins
synchronously with the CK. Therefore, note that during the writing of
data, previously read data is not retained.
An
A2 A1
Address Buffer
Row Decoder
Control
CK
A0
XCS
XWE
Memory Cell Array
Memory Cell Array
Data I/O Buffer
D0
Y0
Data I/O Buffer
D1
Y1
Memory Cell Array
Data I/O Buffer
Dn
Yn
Figure 6-8 Block Diagram of a 1 port RAM (Clock Synchronous Type)
EMBEDDED ARRAY S1X60000 SERIES
DESIGN GUIDE
EPSON
119