S1X60000 Datasheet, PDF (220/358 Pages) Epson Company – EMBEDDED ARRAY

Chapter 9 Circuit Design
Calculation example: Determine whether the magnitude of noise is sufficiently large to
cause malfunction due to the simultaneous operation of outputs under the following voltage
and pin-layout conditions.
• Power supply voltage : 3.3 V/2.5 V
• Input interface
: LVTTL for HV cells
CMOS for LV cells
Pin No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Cells Used
V_SS
HV_DD
LV_DD
HV cells, Type 2
HV cells, Type 3
HV cells, Type 3
HV_DD
LV cells, Type 1
LV cells, Type 3
LV_DD
V_SS
Output Load
Capacitance (pF)
125
100
175
75
150
First, because Tables 9-5 and 9-7 are used, round the output load capacitances up to the
nearest whole value.
(4) 125 pF → 150 pF
(5) 100pF → 100 pF
(6) 175 pF → 200 pF
(8) 75 pF → 100 pF
(9) 150 pF → 150 pF
• Make determination for the closed loop between HVDD’s ((2) to (7))
The HV output cells used in the closed loop between HVDD’s are (4), (5), and (6).
From the input interface and the power supply voltage, make determination using the
coefficients given in Table 9-5.
∑ ^{mk = 0.143 + 0.250 + 0.333 = 0.726}
k
Thus, the result shows that the closed loop between HVDD’s satisfies the determination
criteria.
EMBEDDED ARRAY S1X60000 SERIES
DESIGN GUIDE
EPSON
211