S1X60000 Datasheet, PDF (210/358 Pages) Epson Company – EMBEDDED ARRAY

Chapter 9 Circuit Design
9.10 Restrictions and Constraints on VHDL/Verilog-HDL
Netlist
The VHDL/Verilog-HDL netlist to be interfaced to Epson shall be a pure gate level netlist
(not containing function and description of operation). The restrictions and constraints in
developing Epson ASIC using VHDL/Verilog-XL are as follows.
9.10.1 Common Restrictions and Constraints
(1) Names of external pin (I/O pin)
• Use only upper case letters.
• Number of characters: 2 to 32
• Bus description is prohibited.
• Usable characters: Alphanumeric characters and “_.” Use an alphabetical letter at
the head.
• Examples of prohibited character strings:
2 INPUT: A digit is at the head.
\2INPUT: “\” is at the head.
InputA: Lower case letters are included.
_INPUTA: “_” is at the head.
INA[3:0]: A bus is used for the name of the external pin.
INA[3]: A bus is used for the name of the external pin.
(2) Names of internal pin (including bus net names)
Upper and lower case letters can be used in combination, except the following.
Combinations of the same words expressed in upper and lower case letters, such as
“_RESET_” and “_Reset_.”
• Number of characters: 2 to 32
• Usable characters: Alphanumeric characters, “_”, “_[]_” (Verilog bus blanket), and
“_()_” (VHDL bus blanket) with an alphabetical letter at the head.
(3) Module names
In systems, module names are discriminated between the uppercase and lowercase. In
design rules, however, mixed use of uppercase and lowercase module names is
prohibited.
Example: Mixed use of “AND” and “And”
Because cells are case-sensitive, be careful about upper and lower case when you enter
module names.
(4) Bus description is prohibited at the most significant place of the module.
Examples:
DATA [0:3], DATA [3], and DATA [2] are prohibited.
DATA0, DATA1, and DATA2 are all allowed.
EMBEDDED ARRAY S1X60000 SERIES
DESIGN GUIDE
EPSON
201