S1X60000 Datasheet, PDF (237/358 Pages) Epson Company – EMBEDDED ARRAY

Chapter 10 Circuit Design that Takes Testability into Account
*2: This includes all output and all bi-directional pins other than the DC test
monitor output pin.
• Input characteristic (VIH/VIL) measurement mode
TSTEN
... High
Measured pins ^*3
... Low
Non-measured pin
... High
DC test monitor output pin
... High or Low
*3: All input and all bi-directional pins (except TSTEN) must be tested.
• Leakage current measurement mode
TSTEN
... High
INP0
... High
INP1
... Low
INP2
... High
Measured pins^*4
... High or Low
3-state and Nch open drain pins ... High impedance
*4: This includes all 3-state output and all bi-directional pins other than
INP0-2.
b: Dedicated AC test
• Dedicated AC path measurement mode
TSTEN
... High
INP0
... Low
INP1
... Low
INP2 ^*5
... Change to High or Low
(input signal for the measured device)
INP3 ^*5
... Select High (delay cell delay) or Low
(bypass delay)
(Measured device select pin)
AC test monitor output pin
... Outputs a signal corresponding to input
for INP2.
*5: After selecting the measured device using INP3, change INP2 to High or
Low in the next and subsequent events. In a pattern in which INP2 and
INP3 change state simultaneously, delays cannot be measured accurately.
Refer to Figure 10-3, “Example of the Generation of a Test Pattern When
There is a Test Option.”
c: Macro test
• Macro-test mode
TSTEN
INP0
INP1
INP2
Macro control pin in test mode^*6
Macro watch pin in test mode^*6
... High
... High
... Low
... Low
... Depends on the macro function
... Depends on the macro operation
*6: This pin is assigned for macro control or watch in test mode.
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EMBEDDED ARRAY S1X60000 SERIES
DESIGN GUIDE