EN25QH128A Datasheet, PDF (63/75 Pages) Eon Silicon Solution Inc. – 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH128A
Table 18. AC Characteristics
(T_a = - 40°C to 85°C; V_CC = 2.7-3.6V)
Symbol Alt
Parameter
Min Typ
Max
Unit
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
D.C.
-
104
MHz
F_R
f_C
WRDI, WRSR and Dual Output Fast Read ⁴
Serial Clock Frequency for:
RDSR, Read Burst, Quad I/O Fast Read ⁴
D.C.
-
80
MHz
f_R
t_CH ¹
t_CL1
t_CLCH2
t_CHCL ²
t_SLCH
t_CHSH
t_SHCH
t_CHSL
t_SHSL
t_SHQZ ²
t_CLQX
t_DVCH
t_CHDX
t_HLCH
t_HHCH
t_CHHH
t_CHHL
t_HLQZ ²
t_HHQX ²
t_CLQV
t_WHSL3
t_SHWL3
t_DP ²
t_RES1 ²
t_RES2 ²
t_W
t_PP
t_SE
t_HBE
t_BE
t_CE
t_CSS
t_CSH
t_DIS
t_HO
t_DSU
t_DH
t_HZ
t_LZ
t_V
Serial Clock Frequency for READ, RDID
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time (Relative to CLK)
CS# Active Hold Time (Relative to CLK)
CS# Not Active Setup Time (Relative to CLK)
CS# Not Active Hold Time (Relative to CLK)
CS# High Time for read
CS# High Time for program/erase
Output Disable Time
Output Hold Time
Data In Setup Time
Data In Hold Time
HOLD# Low Setup Time ( relative to CLK )
HOLD# High Setup Time ( relative to CLK )
HOLD# Low Hold Time ( relative to CLK )
HOLD# High Hold Time ( relative to CLK )
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Valid from CLK for Vcc = 2.7 to 3.6v
Output Valid from CLK for Vcc = 3.0 to 3.6v
Write Protect Setup Time before CS# Low
Write Protect Hold Time after CS# High
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
32 KB Block Erase Time
64 KB Block Erase Time
Chip Erase Time
D.C.
-
4
-
4
-
0.1
-
0.1
-
5
-
5
-
5
-
5
-
15
50
-
-
-
0
-
2
-
4
-
5
5
5
5
-
-
20
-
100
-
-
-
-
-
-
-
-
15
-
0.8
-
0.05
-
0.1
0.2
-
45
50
MHz
-
ns
-
ns
-
V / ns
-
V / ns
-
ns
-
ns
-
ns
-
ns
-
ns
ns
6
ns
-
ns
-
ns
-
ns
ns
ns
ns
ns
6
ns
6
ns
8
7
ns
-
ns
-
ns
3
µs
3
µs
1.8
µs
50
ms
5
ms
0.3
s
1
s
2
s
140
s
t_SR
Software Reset ^{WIP = write operation}
-
-
28
µs
Latency
WIP = not in write operation
-
-
0
µs
Note: 1. t_CH + t_CL must be greater than or equal to 1/ f_C
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
4. For PDIP package, the Max speed is 50MHz
This Data Sheet may be revised by subsequent versions
63
or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2014/01/22
www.eonssi.com