EN25QH128A Datasheet, PDF (46/75 Pages) Eon Silicon Solution Inc. – 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH128A
Figure 28. 64KB Block Erase Instruction Sequence Diagram
Figure 28.1 Half Block/Block/Sector Erase Instruction Sequence in QPI Mode
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2014/01/22
www.eonssi.com