EN25QH128A Datasheet, PDF (24/75 Pages) Eon Silicon Solution Inc. – 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH128A
WHDIS bit. The WP# and Hold# Disable bit (WHDIS bit), non-volatile bit, it indicates the WP# and
HOLD# are enabled or not. When it is “0” (factory default), the WP# and HOLD# are enabled. On the
other hand, while WHDIS bit is “1”, the WP# and HOLD# are disabled. No matter WHDIS is “0＂ or
“1＂, the system can executes Quad Input/Output FAST_READ (EBh) or EQPI (38h) command
directly. User can use Flash Programmer to set WHDIS bit as “1＂ and then the host system can let
WP# and HOLD# keep floating in SPI mode.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set
to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register
(SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is
no longer accepted for execution.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Read Information Register (RDIFR) (2Bh)
The Read Information Register (RDIFR) instruction is for reading the value of Information Register. The
Read Information Register can be read at any time (even in program/erase/write status register
condition) and continuously, as shown in Figure 11.
The sequence of issuing RDIFR instruction is: CS# goes low -> sending RDIFR instruction ->
Information Register data out on DO -> CS# goes high.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 11. Read Information register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2014/01/22
www.eonssi.com