EN25QH128A Datasheet, PDF (14/75 Pages) Eon Silicon Solution Inc. – 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH128A
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25QH128A provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Half Block Erase (HBE) / Block Erase (BE) instruction completion or Chip Erase
(CE) instruction completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register Content
Memory Content
BP3 BP2
Bit Bit
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
Protect Areas
0
None
1
Block 255
0
Block 254 to 255
1
Block 252 to 255
0
Block 248 to 255
1
Block 240 to 255
0
Block 224 to 255
1
All
0
None
1
Block 0
0
Block 0 to 1
1
Block 0 to 3
0
Block 0 to 7
1
Block 0 to 15
0
Block 0 to 31
1
All
Addresses
None
FF0000h-FFFFFFh
FE0000h-FFFFFFh
FC0000h-FFFFFFh
F80000h-FFFFFFh
F00000h-FFFFFFh
E00000h-FFFFFFh
000000h-FFFFFFh
None
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
000000h-07FFFFh
000000h-0FFFFFh
000000h-1FFFFFh
000000h-FFFFFFh
Density(KB) Portion
None
64KB
128KB
256KB
512KB
1024KB
2048KB
16384KB
None
64KB
128KB
256KB
512KB
1024KB
2048KB
16384KB
None
Upper 1/256
Upper 2/256
Upper 4/256
Upper 8/256
Upper 16/256
Upper 32/256
All
None
Lower 1/256
Lower 2/256
Lower 4/256
Lower 8/256
Lower 16/256
Lower 32/256
All
This Data Sheet may be revised by subsequent versions
14
or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2014/01/22
www.eonssi.com