EN25QH128A Datasheet, PDF (47/75 Pages) Eon Silicon Solution Inc. – 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH128A
The instruction sequence is shown in Figure 29. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0.
The Chip Erase (CE) instruction is ignored if one, or more blocks are protected.
The instruction sequence is shown in Figure 29.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
Figure 29. Chip Erase Instruction Sequence Diagram
Figure 29.1 Chip Erase Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2014/01/22
www.eonssi.com