EPVP6200 Datasheet, PDF (40/57 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6200
VFD Controller
8 Segment Data Buffers
The ePVP6200 chip provides a total of 256 bytes data RAM. On the other hand, display
Segment Data Buffers can be stored either in the data RAM of 256 bytes sizes (00h~40h) or in
the common registers of Bank 2 and Bank 3 (20h~3Fh).
a) Data RAM Address
00h~38h
39h~3Eh
3Fh
40h
57X8 Segment Data Buffers
6X8 Key Scanning Data Buffers
SW data register
LED data register
b) Common Registers Address
20
Bank0~Bank3
:
Common registers
3F
(32x8 for each bank)
These buffers store display RAM. The display RAM stores the data transmitted from an external device to the
ePVP6200 through the serial interface and is assigned addresses as follows, in units of 8 bits:
b0
b3 b4
b7
X X HL
X X HU
Lower 4 bits
Higher 4 bits
Only the lower 4 bits of the addresses assigned to SEG17 through SEG20 are valid and the
higher 4 bits are ignored.
c) Display Memory Addresses:
34 of 57
Seg1 Seg4
00 HL
03 HL
06 HL
09 HL
0C HL
0F HL
12 HL
15 HL
18 HL
1B HL
1E HL
21 HL
24 HL
11.18.2004 (V1.53)
Seg8
00 HU
03 HU
06 HU
09 HU
0C HU
0F HU
12 HU
15 HU
18 HU
1B HU
1E HU
21 HU
24 HU
Seg12
01 HL
04 HL
07 HL
0A HL
0D HL
10 HL
13 HL
16 HL
19 HL
1C HL
1F HL
22 HL
25 HL
Seg16
Seg20
01 HU
02 HL
DIG1
04 HU
05 HL
DIG2
07 HU
08 HL
DIG3
0A HU
0B HL
DIG4
0D HU
0E HL
DIG5
10 HU
11 HL
DIG6
13 HU
14 HL
DIG7
16 HU
17 HL
DIG8
19 HU
1A HL
DIG9
1C HU
1D HL
DIG10
1F HU
20 HL
DIG11
22 HU
23 HL
DIG12
25 HU
26 HL
DIG13
This specification is subject to change without further notice.