EPVP6200 Datasheet, PDF (27/57 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6200
VFD Controller
Trigger edge is as shown below:
Signal
Trigger
TCC
Time out
COUNTER1 Time out
COUNTER2 Time out
COUNTER3 Time out
COUNTER4 Time out
COUNTER5 Time out
IR
Falling
Rising edge
INT1
Falling edge
INT2
Falling edge
INT3
Falling edge
INT4
Falling edge
7.2.17 R10~R3F (General Purpose Registers)
R10 ~ R1F, R20 ~ R3F (Banks 0 ~ 3) : all are general purpose registers.
7.3 Special Purpose Registers
7.3.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It is not an addressable register.
7.3.2 CONT (Control Register)
CONT register is readable (CONTR) and writable (CONTW).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
P90EG
INT
TS
RETBK
PAB
PSR2
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
Bit 1
PSR1
Bit 0
PSR0
This specification is subject to change without further notice.
11.18.2004 (V1.53) 21 of 57