EPVP6200 Datasheet, PDF (35/57 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6200
VFD Controller
7.5I/O Port
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input"
or "output" pins by the I/O control registers under program control. The I/O data registers and
I/O control registers are both readable and writable. The I/O interface circuit is shown in
Fig.22.
PCRD
QPD
R
C ^CLK
QL
PCWR
PORT
QPD
IOD
R
C ^CLK
QL
PDWR
0M
U
1
X
PDRD
Fig. 8 The Circuit of I/O Port and I/O Control Register
7.6 RESET
A RESET can be caused by any of the following:
1. Power on reset
2. WDT timeout (if enabled and in GREEN or NORMAL mode)
3. /RESET pin pull low
Once a RESET occurs, the following functions are performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
The Watchdog timer and prescaler counter are cleared.
The Watchdog timer is disabled.
The CONT register is set to all "1"
This specification is subject to change without further notice.
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