EPVP6200 Datasheet, PDF (34/57 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6200
VFD Controller
RBF
IOCE bit6 = 1
And “ENI
No function
Interrupt
Interrupt
(jump to Address 8 (jump to Address 8
on Page0)
on Page0)
STB
IOCE bit4 = 1
And “ENI
No function
Interrupt
Interrupt
(jump to Address 8 (jump to Address 8
on Page0)
on Page0)
NOTES: 1. PORT90 interrupt function is controlled by IOCF Bit 3. It is a falling edge or rising edge
trigger (controlled by CONT register Bit7).
2. PORT9 (1~4) interrupt functions are controlled by IOCF Bits 4, 5, 6, & 7). They are falling
edge triggers.
3. STB interrupt source function is controlled by IOCE PAGE0 Bit 4. It is falling edge trigger
after the STB goes low.
7.4 Application notes
1 Call-table instruction:
Because the call-table instruction can only change the Program Counter's bit7 ~
bit0 at each time, only 256 addresses can be searched once.
But each program page contains 1024 addresses, if call each 256 addresses as a
zone, Then each page constitutes by four zones.
When a table overlaps two zones, a bug would occur during address searching.
So the member of program must examine the .LST file at any time, the .LST file
will jot down the information that Assembler generated, for example source code,
the coding of instruction , instruction address, error message etc.
2 Operation requirement for the CPU
The system frequency must adds a latency time ( 14.33 MHz about 250 ms
17.91 MHz about 450 ms.). After RA register was setting, it will offer the stable
system frequency for the operation.
3 The register initial sets to suggest
The register 0X0B of IOC page 0 & page 1 initial sets suggestion as follows
0x0B register value = 0x00
The register 0X0B of R page 0 initial sets suggestion as follows
0x0B register value = 0x00
28 of 57 11.18.2004 (V1.53)
This specification is subject to change without further notice.