EPVP6200 Datasheet, PDF (31/57 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6200
VFD Controller
1
1
0
1:128
1
1
1
1:256
Bit 7 (CNT4S) : COUNTER4 clock source
0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
1 system clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
7.3.6 IOCA
a) PAGE 1 (Clock Source and Prescaler for COUNTER5 )
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
CNT5S C5_PSC2 C5_PSC1 C5_PSC0
-
-
-
-
R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 2 (C5_PSC0 ~ C5_PSC2) : COUNTER5 prescaler ratio
C5_PSC2 C5_PSC1 C5_PSC0 COUNTER4
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 3 (CNT5S) : COUNTER5 clock source
0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
1 system clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
7.3.7 IOCC (PORTC I/O Control)
a) PAGE 0 (PORTC I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IOCC7 IOCC6 IOCC5 IOCC4 IOCC3
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
Bit 2
IOCC2
R/W-1
Bit 1
IOCC1
R/W-1
Bit 0
IOCC0
R/W-1
Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register
0 set the relative I/O pin as output
1 set the relative I/O pin into high impedance
This specification is subject to change without further notice.
11.18.2004 (V1.53) 25 of 57