EPVP6200 Datasheet, PDF (15/57 Pages) ELAN Microelectronics Corp – VFD Controller

ePVP6200
VFD Controller
7.2 Operation Registers Description
7.2.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as indirect address pointer. Any
instruction using R0 as register actually accesses data pointed by the RAM Select Register
(R4).
Example:
Mov A, @0x20
Mov 0x04, A
Mov A, @0xAA
Mov 0x00, A
;store an address at R4 for indirect address
;write data 0xAA to R20 at Bank0 through R0
7.2.2 R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by
CONT register).
Written and read by the program as any other register.
7.2.3 R2 (Program Counter)
The structure is depicted in Fig.3 below.
Generates 8k × 13 external ROM addresses to the relative programming instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
"RET'' ("RETL k," "RETI") instruction loads the program counter with the contents at the top of
stack.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and
tenth bits are cleared to "0''.
"ADD R2, A" allows a relative address to be added to the current PC, and contents of the ninth
and tenth bits are cleared to "0''.
R5(PAGE)
PC ^{A13 A12 A11 A10}
0000
0001
0010
0111
CALL and
INTERRUPT
A9 A8 A7~A0
PAGE0
0000~03FF
PAGE1
0400~07FF
PAGE2
0800~0BFF
RET
RETL
RETI
PAGE7
1C00~1FFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
STACK9
STACK10
STACK11
STACK12
STACK13
STACK14
STACK15
STACK16
INTERRUPT
ACC,R3,R5(PAGE)
restore store
3 bytes register
Fig. 3 Program Counter Organization
This specification is subject to change without further notice.
11.18.2004 (V1.53) 9 of 57