DA9063_17 Datasheet, PDF (98/219 Pages) Dialog Semiconductor – System PMIC for Mobile Application Processors

DA9063
System PMIC for Mobile Application Processors
The switching converters can be enabled/disabled/configured via the power manager and HS 2-
WIRE interface. Writing to Bxxxx_EN/VBxxxx_SEL unconditionally configures the regulator to the
selected mode (enabled/disabled). Reading Bxxxx_EN/VBxxxx_SEL provides the actual state, which
may differ from a previous write (in the case where the regulator state is changed from GPIO or
power sequencer control). All bucks can be controlled with an ID from the power sequencer. If
enabled in DEF_SUPPLY, supplies can be configured to default settings when the sequencer passes
slot 0.
To limit the inrush current, it is recommended to select individual regulators (including LDOs) only
with xxxx_DEF settings.
When powering up, the power sequencer clears VBxxxx_SEL for a buck when it has an ID pointing
to the time slot being processed. This forces the regulator to ramp the output voltage to the value
programmed inside the related register VBxxxx_A.
When powering down (for example, to POWERDOWN mode), sequencer-controlled supplies are
usually disabled but can be configured to remain on by setting Bxxxx_CONF. In the latter case, the
sequencer sets VBxxxx_SEL so that the regulator output voltage is ramped to the value programmed
inside the related register VBxxxx_B. Disabled bucks can switch off their pull-down resistor, see
Section 6.9.5. Before wakeup from POWERDOWN mode (processing time slots from domain
SYSTEM), the sequencer can configure the bucks with default voltage values from OTP and reset
any changed VBxxxx_A settings.
All buck converters provide an optional hardware enable/disable via GPIO1, 2, and 13. A regulator
that has to be enabled/disabled from a GPI port selects this feature via its control Bxxxx_GPI. A
change of the output voltage from the state of a GPI is enabled via control VBxxxx_GPI. After
detecting a rising or falling edge at the GPI, the DA9063 configures the enabled regulators with the
status of GPI1, GPI2, or GPI13 (the event bit E_GPI1, E_GPI2 or E_GPI13 is automatically cleared).
A parallel write access to the regulator control registers is delayed and later overrides the HW
configuration. The sequencer does not change regulator settings enabled for GPI control. Powering
down to RESET mode automatically disables all buck converters. When the output of a buck
converter is combined with a parallel low power LDO, its pull-down resistor needs to be disabled via
Bxxxx_PD_DIS. Otherwise its output is discharged to GND when being disabled.
To allow DVC transitions under load, the buck current limit should be configured at least 40% higher
than the required maximum continuous output current. See Table 47 as a guide to determining this
limit.
Table 47: Selection of Buck Current Limit from Coil Parameters
Min. ISAT
(mA)
Frequency
(MHz)
Buck Current Limit
(mA)
3800
3
3400
3100
3
2800
2400
3
2100
1700
3
1700
Max. Output Current
(mA)
2400
2000
1500
1200
To ensure correct regulation, the buck converters require the supply voltage to be 0.7 V higher than
the output voltage. As this is not always possible at higher output voltage settings, the converters
BUCKMEM, BUCKIO, and BUCKPERI provide a follower mode where the electrical characteristics of
the DC-DC converter no longer apply, but instead the PMOS output driver is fully-on and the output
voltage simply follows the dropping input voltage. There will be a voltage drop between the buck
VDD supply and the output which results from the on-resistance of the buck PMOS driver and the
coil, with the voltage drop magnitude being depending on load current. Bucks running in follower
mode will temporarily stop switching and by that process will generate PWM mode 3 MHz sub-
harmonics.
Datasheet
CFR0011-120-00
DA9063_2v1
98 of 219
23-Mar-2017
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