DA9063_17 Datasheet, PDF (24/219 Pages) Dialog Semiconductor – System PMIC for Mobile Application Processors

DA9063
System PMIC for Mobile Application Processors
Parameter
Symbol Test Conditions
Min
Typ
Max Unit
CLK high time
CLKH
0.26
µs
2-WIRE CLK and DATA rise
time
(input requirement)
1000
ns
2-WIRE CLK and DATA fall
time
(input requirement)
300
ns
Data set-up time
DST
50
ns
Data hold-time
DHT
0
ns
Data valid time
0.45
µs
Data valid time acknowledge
0.45
µs
Stop condition set-up time
TSS
0.26
µs
High Speed Mode
CLK clock frequency
Requires VDDIO ≥ 1.8 V
0
Note 1
3400 kHz
Start condition set-up time
160
ns
Start condition hold time
STH
160
ns
CLK low time
CLKL
160
ns
CLK high time
CLKH
60
ns
2-WIRE CLKH and SDAH
rise/fall time
Input requirement
160
ns
Data set-up time
DST
10
ns
Data hold-time
DHT
0
ns
Stop condition set-up time
TSS
160
ns
Note 1 Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled
5.7 4-Wire Control Bus
nCS
21
4
5
SK
10
SI
A6
A5 A4
7
6
R/W
SO
BIT 7
Address
R/W
Figure 8: 4-Wire Bus Timing
Note 1 The above timing is valid for active-low and high CS
3 11
BIT 1 LSB
8
9
BIT 1 LSB
DATA
Datasheet
CFR0011-120-00
DA9063_2v1
24 of 219
23-Mar-2017
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