DA9063_17 Datasheet, PDF (66/219 Pages) Dialog Semiconductor – System PMIC for Mobile Application Processors

DA9063
System PMIC for Mobile Application Processors
6.1.9 GP_FB2, General Purpose Signal 2 (PWR_OK/KEEP_ACT)
The GP_FB2 port supports two different modes selected by the control PM_FB2_PIN.
Table 38: PM_FB2_PIN Settings
PM_FB2_PIN
0
1
Description
PWR_OK. In this mode the port is a regulator status indicator. The port is an open drain output
asserted if none of the selected regulators are out-of-range. The regulator monitoring via ADC
must be enabled and all regulators to be monitored must have supervision enabled with the
selected persistence, and mask bit M_REG_UVOV must be asserted. In case at least one of
the supervised regulators is out-of-range or regulator monitoring is disabled, the PWR_OK
signal is low.
KEEP_ACT. If enabled, every assertion of the port (rising to active level edge sensitive) sets
the watchdog trigger, similar to writing to bit WATCHDOG via the power manager bus. The
host has to release KEEP_ACT before the next assertion during continuous watchdog
supervision (if enabled). The minimum assertion and de-assertion cycle time is 150 µs.
The output active level (and driver type) can be configured via GP_FB2_TYPE.
Alternatively, with BCORE_MERGE = 1, FB in register BCORE1_CFG set to 0b000 and
MERGE_SENSE = 0, the GP_FB2 pin becomes a voltage feedback signal for BUCKCORE.
6.1.10 GP_FB3, General Purpose Signal 3 (OUT32K_2/nVIB_BRAKE)
The GP_FB3 port supports two different modes selected by the control PM_FB3_PIN.
Table 39: PM_FB3_PIN Settings
PM_FB3_PIN
0
1
Description
OUT32K_2. This provides a second 32K signal output (push-pull).
nVIB_BRAKE. If LDO8 is configured as a vibrator motor driver, GP_FB3 can be configured to
provide an external brake signal. The vibrator motor can be started or stopped by a change in
the level on the nVIB_BRAKE signal. If the port is not used as a brake command, the vibration
motor runs continuously at the speed configured by VIB_SET.
GP_FB3_TYPE defines the active level.
6.1.11 Supply Rail Fault (nVDD_FAULT)
nVDD_FAULT is a signal to the host processor to indicate a supply voltage (V_SYS) low status.
Asserting nVDD_FAULT indicates that the main supply input voltage is low
(V_SYS < VDD_FAULT_UPPER) and therefore informs the host processor that the power will shut
down soon. The event control E_VDD_WARN is asserted and the nIRQ line is asserted (if not
masked). During POWER_DOWN mode a wakeup is generated. After that the processor may
operate for a limited time from the remaining battery capacity or the processor may enter a standby
mode. As long as V_SYS does not recover, the host can re-enable the nIRQ line by asserting
M_VDD_WARN or clearing E_VDD_WARN. The DA9063 starts a fault power down sequence. If
V_SYS drops below VDD_FAULT_LOWER, the DA9063 enters RESET mode. The
VDD_FAULT_LOWER threshold and the hysteresis on VDD_FAULT_UPPER are OTP configurable.
The nVDDFAULT port can alternatively be controlled by the state of the debounced V_SYS monitor
inside the ADC (selected via GPIO12_PIN). The signal is asserted when the ADC detects three
consecutive results below the configurable threshold VSYS_MON (it becomes passive after three
consecutive results above VSYS_MON). This provides a variable power good signal to trigger boot
activities on external ICs.
The active level/debounce, wakeup, and IO supply voltage can be selected via the controls
GPIO12_MODE, GPIO12_WEN and GPIO12_TYPE, respectively.
Datasheet
CFR0011-120-00
DA9063_2v1
66 of 219
23-Mar-2017
© 2017 Dialog Semiconductor