DA9063_17 Datasheet, PDF (78/219 Pages) Dialog Semiconductor – System PMIC for Mobile Application Processors

DA9063
System PMIC for Mobile Application Processors
6.5.4 Powering Down
When the DA9063 is powering down, the sequencer disables the supplies in reverse order and
timing, asserts READY during sequencing, and triggers E_SEQ_RDY on reaching the target
sequencer slot. Supplies that are configured to stay on (LDO<x>_CONF, B<x>_CONF,
xxx_SW_CONF bit is set) are not disabled and are configured with the voltage setting from register
VB<x>_B/VLDO<x>_B when the related time slot/ID is processed. The state of the regulators that
are enabled for GPI control will not be changed by the sequencer when processing the related ID.
This also applies for the selection of the related V<x>_A or V<x>_B voltage control register in case a
regulator is enabled for GPI voltage selection.
If powering down is initiated by clearing POWER1_EN, the sequencer stops controlling IDs before
the domain pointer POWER_END is reached. If POWER_EN is cleared, the domain POWER1 is
powered down followed by POWER before the sequencer reaches pointer SYSTEM_END. These
modes are used to temporarily disable optional features of a running application for reduced power
(sleep mode).
If SYSTEM_EN is cleared the sequencer processes all IDs lower than the pointer position down to
slot 0. The sequencer can be forced to stop the intended power down sequence prior to maturity at
pointer position PART_DOWN via an asserted control STANDBY (PART_DOWN has to point into
domain SYSTEM). In these cases the power sequencer has reached the application’s
POWERDOWN mode (hibernate/standby), which enables the option to reset regulator settings for
the consecutive power-up sequence from OTP (enabled by OTPREAD_EN).
Wakeup events are enabled when the sequencer reaches slot 0 or pointer PART_DOWN (ignored
outside of POWERDOWN mode). The assertion of nIRQ from events during POWERDOWN mode
may be delayed until ACTIVE mode is reached the next time if configured by nIRQ_MODE. During
processing slot 0, all supplies pointing into this step with a cleared control
Bxxx_CONF/LDOxx_CONF/xxx_SW_CONF are disabled, otherwise the regulator voltage is changed
to VBxxx_B/VLDOxx_B (if bit DEF_SUPPLY is asserted). Asserting control register bit SHUTDOWN
first powers down to slot 0 and then forces the DA9063 into RESET mode. Autonomous features
such as the 32K output buffer or the Auto-ADC measurement can be disabled temporarily for
POWERDOWN mode via register PD_DIS. The timing for processing PD_DIS can be defined by
selecting a step inside the sequence. Features asserted in PD_DIS are (re-)enabled when PD_DIS is
processed during a power-up sequence.
Control nRES_MODE enables the assertion of nRESET before executing a power-down sequence
and starting the reset timer during the consecutive powering up. This is also true for partial
POWERDOWN mode, when the sequencer powers down to pointer position PART_DOWN. The
reset timer starts to run from the selected RESET_EVENT and releases the nRESET port after the
reset timer expires.
6.5.5 User Programmable Delay
A conditional mode transition can be achieved using ID WAIT_STEP. If pointing into the power
sequence the progress of an initiated mode transition can be synchronized, for example with the
state of a host. This is indicated by toggling the signal at GPI10 to its configured active state. A safety
timeout of 500 ms can be selected in TIME_OUT to trigger a power-down to RESET mode (including
the assertion of WAIT_SHUT inside register FAULT_LOG) if E_GPI10 is not asserted in time. The ID
WAIT_STEP provides an alternate timer mode, selected by WAIT_MODE and configured by
WAIT_TIME, which provides a delay timer for a selected sequencer step. To enable symmetric
sequence behavior, ID WAIT_STEP should not share a sequencer slot with other IDs. In the case of
a shutdown sequence to RESET mode any waiting/delay at ID WAIT_STEP is skipped.
Datasheet
CFR0011-120-00
DA9063_2v1
78 of 219
23-Mar-2017
© 2017 Dialog Semiconductor