DS8007 Datasheet, PDF (25/41 Pages) Dallas Semiconductor – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Hardware Status Register (HSR)
7
Address 0Fh
—
R-0
6
PRTLB
R-0
5
PRTLA
R-0
4
SUPL
R-1
3
PRLB
R-0
2
1
0
PRLA
INTAUXL
PTL
R-0
R-0
R-0
R = unrestricted read, W = unrestricted write, -n = value after reset, x = always reflects state of external device pin. This register is
reset to 0uuuxxxub on RIU = 0.
Note: A minimum of 2µs is needed between successive reads of the HSR to allow for hardware updates. In addition, a minimum of
2µs is needed between reads of the HSR and activation of card A, card B, or the AUX card.
Bit 7: Reserved.
Bit 6: Protection Card Interface B Status Bit
(PRTLB). This bit is set to 1 when a fault has been
detected on card reader interface B. A fault is defined
as detection of a short-circuit condition on either the
RSTB or V_CCB pin as given by DC specs I_RST(SD) and
I_CC(SD). The INT signal is asserted at logic 0 (active)
while this bit is set. This bit returns to 0 after any HSR
read, unless the condition persists.
Bit 5: Protection Card Interface A Status Bit
(PRTLA). This bit is set to a 1 when a fault has been
detected on card reader interface 1. A fault is defined
as detection of a short-circuit condition on either the
RSTA or V_CCA pin as given by DC specs I_RST(SD) and
I_CC(SD). The INT signal is asserted at logic 0 (active)
while this bit is set. This bit returns to 0 after any HSR
read, unless the condition persists.
Bit 4: Supervisor Latch (SUPL). This bit is set to 1
when V_DD < V_RST or when a reset is caused by exter-
nally driving the DELAY pin < 1.25V. At this time the
INT signal is asserted at logic 0 (active). This bit returns
to 0 only after an HSR read outside the alarm pulse.
Bit 3: Presence Latch B (PRLB). This bit is set to 1
when a level change has been detected on the PRESB
pin of card interface B. The INT signal is asserted at
logic 0 (active) while this bit is set. This bit returns to 0
after any HSR read.
Bit 2: Presence Latch A (PRLA). This bit is set to 1
when a level change has been detected on the PRESA
pin of card interface A. The INT signal is asserted at
logic 0 (active) while this bit is set. This bit returns to 0
after any HSR read.
Bit 1: INTAUX Latch (INTAUXL). This bit is set to 1
when a 0 → 1 or a 1 → 0 level change has been detect-
ed on the INTAUX pin. This bit remains set, regardless
of further level changes on the INTAUX pin until cleared
to 0 by any HSR read.
Bit 0: Protection Thermal Latch (PTL). This bit is set
to 1 when excessive heating (approximately +150°C or
greater) is detected. The INT signal is asserted at logic
0 (active) while this bit is set. This bit returns to 0 after
any HSR read, unless the condition persists.
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