DS8007 Datasheet, PDF (16/41 Pages) Dallas Semiconductor – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Card Select Register (CSR)
Address 00h
7
CSR7
R-0
6
CSR6
R-0
5
CSR5
R-1
4
CSR4
R-1
3
RIU
RW-0
2
SC3
RW-0
1
SC2
RW-0
0
SC1
RW-0
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00110uuub on RIU = 0.
Bits 7 to 4: Identification Bits (CSR7 to CSR4). These
bits provide a method for software to identify the device
as follows:
0011 = DS8007 revision Ax
Bit 3: Reset ISO UART (RIU). When this bit is cleared
(0), most of the ISO UART registers are reset to their
initial values. This bit must be cleared for at least 10ns
prior to initiating an activation sequence. This bit must
be set (1) by software before any action on the UART
can take place.
Bits 2 to 0: Select Card Bits (SC3 to SC1). These bits
determine which IC card interface is active as shown
below. Only one bit should be active at any time, and
no card is selected after reset (i.e., SC3–SC1 = 000b).
Other combinations are invalid.
000 = No card is selected.
001 = Card A is selected.
010 = Card B is selected.
100 = AUX card interface is selected.
Clock Configuration Register (CCR)
7
Address 01h
—
R-0
6
5
4
3
2
1
0
—
SHL
CST
SC
AC2
AC1
AC0
R-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00uuuuuub on RIU = 0.
Bits 7 and 6: Reserved.
Bit 5: Stop High or Low (SHL). This bit determines if
the card clock stops in the low or high state when the
CST bit is active. It forces the clock to stop in a low
state when SHL = 0 or in a high state when SHL = 1.
Bit 4: Clock Stop (CST). For an asynchronous card,
this bit allows the clock to the selected card to be
stopped. When this bit is set (1), the card clock is
stopped in the state determined by the SHL bit. When
this bit is cleared (0), the card clock operation is
defined by CCR bits AC2–AC0.
Bit 3: Synchronous Clock (SC). For a synchronous
card, the card clock is controlled by software manipu-
lation of this SC, and the contact CLK is the copy of the
value in this bit. In synchronous transmit mode, a write
to the UTR results in the least significant bit (LSb) of the
data written to the UTR being driven out on the I/Ox
pin. In synchronous receive mode, the state of the I/Ox
pin can be read from the LSb of the URR.
Bits 2 to 0: Alternating Clock Select (AC2 to AC0).
These bits select the frequency of the clock provided to
the active card interface and to the UART for the ele-
mentary time unit (ETU) generation as shown below. All
frequency changes are synchronous so that there are
no spikes or unwanted pulse widths during transitions.
f_INT is the frequency of the internal oscillator.
AC2–AC0
000 = f_XTAL
001 = f_XTAL / 2
010 = f_XTAL / 4
011 = f_XTAL / 8
1xx = f_INT / 2
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