DS8007 Datasheet, PDF (15/41 Pages) Dallas Semiconductor – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Control Registers
Special control registers that the host computer/micro-
controller accesses through the parallel bus manage
most DS8007 features. Many of the registers, although
only mentioned once in the listing, are duplicated for
each card interface. The PDR, GTR, UCR1, UCR2, and
CCR registers exist separately for each of the three
card interfaces. The PCR register is provided only for
card interface A and card interface B.
The specific register to be accessed is controlled by
the current setting of the SC3–SC1 bits in the Card
Select Register. For example, there are three instances
of the UART Control Register 1 (UCR1) at address 06h.
If the SC3–SC1 bits are configured so that card A is
selected, then all reads and writes to address 06h only
affect card A. If SC3–SC1 are changed to select card
B, then all reads and writes to address 06h only affect
card B, etc.
In addition, some registers have different functions
based on whether the register is being read from or writ-
ten to. An example of this are the UART Receive
(URR)/UART Transmit (UTR) registers located at address
0Dh. Although they share the same address, during read
operations the receive register is read, and write opera-
tions go to a separate transmit register. This selection
requires no extra configuration by the software.
Table 1. Special Function Register Map
ADDRESS
(HEX)
REGISTER
NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3 BIT 2
BIT 1 BIT 0 RESET
RIU = 0*
00
CSR
R/W CSR7 CSR6 CSR5 CSR4 RIU
SC3
SC2 SC1 0011 0000 0011 0uuu
01
CCR R/W —
—
SHL CST
SC
AC2 AC1 AC0 0000 0000 00uu uuuu
02
PDR
R/W PD7 PD6 PD5
PD4
PD3 PD2
PD1 PD0 0000 0000 uuuu uuuu
03
UCR2
R/W
—
DISTBE/
RBF
DISAUX
PDWN
SAN AUTOC CKU
PSC 0000 0000 uuuu uuuu
05
GTR
R/W GTR.7 GTR.6 GTR.5 GTR.4 GTR.3 GTR.2 GTR.1 GTR.0 0000 0000 uuuu uuuu
06
UCR1 R/W FTE0 FIP
— PROT T/R LCT
SS CONV 0000 0000 0uuu 00uu
07
PCR
R/W —
—
C8
C4
1V8 RSTIN 3V/5V START 0011 0000 0011 uuuu
08
TOC
R/W TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 0000 0000 0000 0000
09
TOR1
W TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 0000 0000 uuuu uuuu
0A
TOR2
W TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8 0000 0000 uuuu uuuu
0B
TOR3
W TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16 0000 0000 uuuu uuuu
0C
MSR
R CLKSW FER
BGT CRED PRB
PRA INTAUX ^TBE/ 0101 0000 u1u1 uuu0
RBF
0C
FCR
W
— PEC2 PEC1 PEC0 FTE1 FL2
FL1 FL0 0000 0000 0uuu 0uuu
0D
URR
R UR7 UR6 UR5 UR4 UR3 UR2 UR1 UR0 0000 0000 0000 0000
0D
UTR
W UT7 UT6
UT5
UT4
UT3 UT2
UT1 UT0 0000 0000 0000 0000
0E
USR
R TO3 TO2 TO1
EA
PE
OVR
FER ^TBE/ 0000 0000 0000 0000
RBF
0F
HSR
R
— PRTLB PRTLA SUPL PRLB PRLA INTAUXL PTL 0001 0000 0uuu xxxu
* u = unchanged, x = always reflects state of external device pin, even when RIU = 0.
Note: Writes to unimplemented bits have no effect. Reads of unimplemented bits return 0.
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