DS8007 Datasheet, PDF (17/41 Pages) Dallas Semiconductor – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
Programmable Divider Register (PDR)
Address 02h
7
PD7
RW-0
6
PD6
RW-0
5
PD5
RW-0
4
PD4
RW-0
3
PD3
RW-0
2
PD2
RW-0
1
PD1
RW-0
0
PD0
RW-0
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
Bits 7 to 0: Programmable ETU Divider Register Bits
7 to 0 (PD7 to PD0). These bits, in conjunction with the
defined UART input clock (based upon CKU,
AC2–AC0) and the prescaler selection (PSC bit), are
used to define the ETU for the UART when interfaced to
the associated card interface. The output of the
prescaler block is further divided according to the
PD7–PD0 bits as follows:
• ETU = Prescaler output / (PD7–PD0), when PD7–PD0
= 02h–FFh
• ETU = Prescaler output / 1, when PD7–PD0
= 00h–01h
• Prescaler output / 256 is not supported
UART Control Register 2 (UCR2)
Address 03h
7
6
5
—
DISTBE/RBF DISAUX
R-0
RW-0
RW-0
4
PDWN
RW-0
3
SAN
RW-0
2
AUTOC
RW-0
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
1
CKU
RW-0
0
PSC
RW-0
Bit 7: Reserved.
Bit 6: Disable TBE/RBF Interrupt (DISTBE/RBF). This
bit controls whether the TBE/RBF flag can generate an
interrupt on the INT pin. When this bit is cleared to 0,
an interrupt is signaled on the INT pin in response to
the TBE/RBF flag getting set. When DISTBE/RBF is set
to 1, interrupts are not generated in response to the
TBE/RBF flag. Disabling the TBE/RBF interrupt can
allow faster communication speed with the card, but
requires that a copy of TBE/RBF in register MSR be
polled to not lose priority interrupts that can occur in
register USR.
Bit 5: Disable Auxiliary Interrupt (DISAUX). This bit
controls whether the external INTAUX pin can generate
an interrupt on the INT output pin. When this bit is
cleared to 0, a change on the INTAUX input pin results
in assertion of the INT output pin. When DISAUX is set
to 1, a change on INTAUX does not result in assertion
of the INT output pin. The INTAUXL bit is set by a
change on the INTAUX pin independent of the DISAUX
bit state. Since the INTAUX bit is set independent of the
DISAUX bit, it is advisable to read HSR (thus clearing
INTAUX) prior to clearing DISAUX to avoid an interrupt
on the INT pin. To avoid an interrupt when selecting a
different card, the DISAUX bit should be set to 1 in all
UCR2 registers.
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