DS8007 Datasheet, PDF (19/41 Pages) Dallas Semiconductor – Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface
UART Control Register 1 (UCR1)
7
6
5
4
3
2
1
Address 06h
FTE0
FIP
—
PROT
T/R
LCT
SS
R-0
RW-0
R-0
RW-0
RW-0
RW-0
RW-0
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu00uub on RIU = 0.
0
CONV
RW-0
Bit 7: FIFO Threshold Enable 0 (FTE0). When this bit
and the FTE1 (FCR.3) bit are set, the programmable
FIFO threshold feature is enabled. This bit always
reads 0 for compatibility.
Bit 6: Force Inverse Parity (FIP). When this bit is con-
figured to 0, the correct parity is transmitted with each
character, and receive characters are checked for the
correct parity. When FIP = 1, an inverse parity bit is
transmitted with each character and correctly received
characters are NAK’d.
Bit 5: Reserved. This bit must be left 0. Setting this bit
to 1 causes improper device operation.
Bit 4: Protocol Select (PROT). This bit is set to 1 by
software to select the asynchronous T = 1 protocol and
is cleared to 0 to select the T = 0 protocol.
Bit 3: Transmit/Receive (T/R). This bit should be set
by software to operate the UART in transmit mode.
When this bit is changed from 0 to 1 (UART changed
from receive to transmit mode), hardware sets the
USR.RBF/TBE bit, indicating an empty transmit buffer.
The T/R bit is automatically cleared to 0 following suc-
cessful transmission if UCR1.LCT is configured to 1
prior to the transmission. This bit cannot be written to
when RIU = 0 (holding in reset).
Bit 2: Last Character to Transmit (LCT). This bit is
optionally set by software prior to writing the last char-
acter to be transmitted to the UART transmit register
(UTR). If LCT is set to 1 prior to writing to UTR, hard-
ware resets the LCT, T/R, and TBE/RBF bits following a
successful transmission. Setting this bit to 1 allows
automatic change to the reception mode after the last
character is sent. This bit can be set during and before
the transmission. This bit cannot be written to when RIU
= 0 (holding in reset).
Bit 1: Software Convention Setting (SS). This bit
should be set by software prior to ATR to allow automat-
ic convention detection. Hardware automatically resets
the SS bit at 10.5 ETU after the detection of the start bit
of the first character of the ATR.
Bit 0: Convention (CONV). This bit defines the charac-
ter decoding convention of the ISO UART. If CONV = 1,
the convention is direct. If CONV = 0, the convention is
inverted. If automatic convention detection is enabled
(AUTOC = 0), hardware detects the character conven-
tion and configures the CONV bit appropriately at 10.5
ETU. Otherwise (AUTOC = 1), software must configure
the CONV bit.
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