S6E2H4 Datasheet, PDF (92/160 Pages) SPANSION – fpu built-in

S6E2H4 Series
Separate Bus Access Synchronous SRAM Mode
Parameter
Address delay time
MCSX delay time
MOEX delay time
Data set up
→MCLK↑ time
MCLK↑→
Data hold time
MWEX delay time
MDQM[1:0]
delay time
MCLK↑→
Data output time
MCLK↑→
Data hold time
Symbol
tAV
tCSL
tCSH
tREL
tREH
tDS
tDH
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
Pin Name
MCLK,
MAD[24:0]
MCLK,
MCSX[7:0]
MCLK,
MOEX
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
MCLK,
MWEX
MCLK,
MDQM[1:0]
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
Note:
− When the external load capacitance CL = 30 pF
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Max
Unit
9
1
12
ns
9
1
ns
12
9
1
ns
12
9
1
12
ns
9
1
ns
12
19
-
ns
37
0
-
ns
9
1
ns
12
9
1
ns
12
1
9
ns
12
9
1
ns
12
MCLK+18
MCLK+1
ns
MCLK+24
18
1
ns
24
Document Number: 001-98941 Rev.*B
Page 92 of 160