S6E2H4 Datasheet, PDF (42/160 Pages) SPANSION – fpu built-in

S6E2H4 Series
Pin Function Pin Name
Function Description
Reset
Mode
INITX
MD1
MD0
External Reset Input pin.
A reset is valid when INITX=L.
Mode 1 pin.
During serial programming to Flash
memory, MD1=L must be input.
Mode 0 pin.
During normal operation, MD0=L must be
input. During serial programming to Flash
memory, MD0=H must be input.
Power
VCC Power supply Pin
GND
VSS GND Pin
Clock
ADC
Power
VBAT
Power
ADC
GND
C pin
X0
X1
X0A
X1A
CROUT_0
CROUT_1
AVCC
AVRL
AVRH
VBAT
AVSS
C
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock output
port
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference voltage
input pin
A/D converter analog reference voltage
input pin
VBAT power supply pin.
Backup power supply (battery etc.) and
system power supply.
A/D converter and D/A converter
GND pin
Power supply stabilization capacity pin
LQFP
120
38
Pin No
LQFP LQFP
100 80
33
23
56
46
36
57
47
37
1
1
1
31
26
-
46
41
31
61
51
-
91
76
61
117 97
77
107 92
-
30
25
20
45
40
30
60
50
40
90
75
60
120 100 80
-
-
-
58
48
38
59
49
39
39
34
24
40
35
25
87
72
58
113 93
73
70
60
49
72
62
51
73
63
52
43
38
28
71
61
50
44
39
29
FBGA
121
L3
L8
K9
B1
K1
K7
K11
A10
A4
A6
L1
L7
L11
A11
A1
K10
L9
L10
L4
K4
C10
B4
J11
G11
F11
L5
H11
L6
Notes:
− While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 001-98941 Rev.*B
Page 42 of 160