S6E2H4 Datasheet, PDF (89/160 Pages) SPANSION – fpu built-in

S6E2H4 Series
12.4.9 External Bus Timing
External Bus Clock Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Max
Output frequency
tCYCLE
MCLKOUT*¹
VCC ≥ 4.5 V
VCC < 4.5 V
-
-
50*²
32*³
MHz
MHz
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual
Main part(MN709-00001).
*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100 MHz.
*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64 MHz.
0.8 × Vcc
MCLK
t_CYCLE
0.8 × Vcc
External Bus Signal Input/output Characteristics
Parameter
Signal input characteristics
Signal output characteristics
Symbol
VIH
VIL
VOH
VOL
Conditions
-
Value
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
Unit
V
V
V
V
(VCC = 2.7V to 5.5V, VSS = 0V)
Remarks
VIH
VIH
Signal input
VIL
VIL
VOH
VOH
Signal output
VOL
VOL
Document Number: 001-98941 Rev.*B
Page 89 of 160