S6E2H4 Datasheet, PDF (124/160 Pages) SPANSION – fpu built-in

S6E2H4 Series
High-speed Synchronous Serial (SPI = 1, SCINV = 1)
Parameter
Internal shift clock
operation
SCK↓→SOT delay time
SIN→SCK↑
setup time
SCK↑→SIN hold time
SOT→SCK↑ delay time
Symbol Pin Name Conditions
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Internal shift
clock
operation
VCC < 4.5 V
Min
Max
4tCYCP
-
-10
+10
14
-
12.5*
5
-
2tCYCP – 10
-
Serial clock L pulse width
tSLSH
SCKx
2tCYCP – 5
-
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Min
Max
Unit
4tCYCP
-
ns
-10
+10 ns
12.5
-
ns
5
-
ns
2tCYCP – 10
-
ns
2tCYCP – 5
-
ns
Serial clock H pulse width tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
External shift
-
15
-
15
ns
SIN→SCK↑
setup time
clock
tIVSHE
SCKx,
SINx
operation
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
SCK rising time
tF
SCKx
tR
SCKx
-
5
-
5
ns
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the following pins.
− No chip select: SIN4_1, SOT4_1, SCK4_1
− Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 001-98941 Rev.*B
Page 124 of 160