S6E2H4 Datasheet, PDF (132/160 Pages) SPANSION – fpu built-in

S6E2H4 Series
When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
VCC < 4.5 V
Min
Max
VCC ≥ 4.5 V
Min
Max
Unit
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
SCS↑→SCK↑setup time
tCSSI
tCSHI
tCSDI
Internal shift
clock
operation
(*1)-20
(*2)+0
(*3)-20
+5tCYCP
(*1)+0
(*2)+20
(*3)+20
+5tCYCP
(*1)-20
(*2)+0
(*3)-20
+5tCYCP
(*1)+0
ns
(*2)+20
ns
(*3)+20
+5tCYCP
ns
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↓→SCS↓ hold time
tCSHE _{External shift}
0
-
0
-
ns
SCS deselect time
tCSDE
clock
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
operation
-
25
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main
part(MN709-00001).
− When the external load capacitance CL = 30 pF.
Document Number: 001-98941 Rev.*B
Page 132 of 160