S6E2H4 Datasheet, PDF (102/160 Pages) SPANSION – fpu built-in

S6E2H4 Series
12.4.11 CSIO Timing
Synchronous Serial (SPI = 0, SCINV = 0)
Parameter
Serial clock cycle time
SCK↓→SOT delay time
SIN→SCK↑
setup time
SCK↑→SIN hold time
Serial clock L pulse width
Serial clock H pulse width
SCK↓→SOT delay time
SIN→SCK↑
setup time
SCK↑→SIN hold time
SCK falling time
SCK rising time
Symbol
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
tF
tR
Pin Name Conditions
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Internal shift
clock
operation
External shift
clock
operation
VCC < 4.5 V
Min
Max
4tCYCP
-
- 30
+ 30
50
-
0
-
2tCYCP - 10
-
tCYCP + 10
-
-
50
10
-
20
-
-
5
-
5
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Min
Max
Unit
4tCYCP
-
ns
- 20
+ 20
ns
30
-
ns
0
-
ns
2tCYCP - 10
-
ns
tCYCP + 10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 001-98941 Rev.*B
Page 102 of 160