CY7C1302CV25 Datasheet, PDF (8/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

PREMILINARY
CY7C1302CV25
Switching Characteristics Over the Operating Range (continued)^[17]
Cypress Consortium
Parameter Parameter
Description
-167
-133
-100
Min. Max. Min. Max. Min. Max. Unit
Hold Times
t_HA
t_HA
t_HC
t_HC
t_HD
t_HD
Output Times
Address Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
Control Signals Hold after Clock (K and K) Rise 0.7
0.8
1.0
ns
(RPS, WPS, BWS₀, BWS₁)
D_[17:0] Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
t_CO
t_CHQV
C/C Clock Rise (or K/K in single clock mode) to
2.5
3.0
3.0 ns
Data Valid
t_DOH
t_CHQX
Data Output Hold after Output C/C Clock Rise 1.2
1.2
1.2
ns
(Active to Active)
t_CHZ
t_CLZ
t_CHZ
t_CLZ
Clock (C and C) Rise to High-Z (Active to High-Z)^{[19, 20]}
2.5
3.0
3.0 ns
Clock (C and C) Rise to Low-Z^{[19, 20]}
1.2
1.2
1.2
ns
Notes:
19. t_CHZ, t_CLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature t_CHZ is less than t_CLZ and, t_CHZ less than t_CO.
Document #: 38-05491 Rev. *A
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