CY7C1302CV25 Datasheet, PDF (2/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

PREMILINARY
CY7C1302CV25
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
CY7C1302CV25
-167
167
750
CY7C1302CV25
-133
133
650
CY7C1302CV25
-100
100
550
Unit
MHz
mA
Pin Configuration–CY7C1302CV25 (Top View)
1
2
3
4
5
A
NC Gnd/144M NC/36M WPS BWS₁
B
NC
Q9
D9
A
NC
C
NC
NC
D10
VSS
A
D
NC
D11
Q10
VSS
VSS
E
NC
NC
Q11 VDDQ VSS
F
NC
Q12
D12 VDDQ VDD
G
NC
D13
Q13 VDDQ VDD
H
NC
VREF VDDQ VDDQ VDD
J
NC
NC
D14 VDDQ VDD
K
NC
NC
Q14 VDDQ VDD
L
NC
Q15
D15 VDDQ VSS
M
NC
NC
D16
VSS
VSS
N
NC
D17
Q16
VSS
A
P
NC
NC
Q17
A
A
R
TDO
TCK
A
A
A
6
K
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
8
9
10
11
NC
RPS NC/18M Gnd/72M NC
BWS₀
A
NC
NC
Q8
A
VSS
NC
Q7
D8
VSS
VSS
NC
NC
D7
VSS VDDQ NC
D6
Q6
VDD VDDQ NC
NC
Q5
VDD VDDQ NC
NC
D5
VDD VDDQ VDDQ VREF
ZQ
VDD VDDQ NC
Q4
D4
VDD VDDQ NC
D3
Q3
VSS VDDQ NC
NC
Q2
VSS
VSS
NC
Q1
D2
A
VSS
NC
NC
D1
A
A
NC
D0
Q0
A
A
A
TMS
TDI
Pin Definitions
Name
D_[17:0]
WPS
BWS₀, BWS₁
A
Q_[17:0]
RPS
C
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Outputs-
Synchronous
Input-
Synchronous
Input-
Clock
Description
Data input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D_[17:0] to be ignored.
Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Write operations. Used to select which byte is written into the device during the current portion
of the Write operations. Bytes not written remain unaltered.
BWS₀ controls D_[8:0] and BWS₁ controls D_[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address)
clocks for active Read and Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x
18). These inputs are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K when in single clock mode. When the Read port is deselected, Q_[17:0] are automatically
three-stated.
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst
of two sequential transfers.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Document #: 38-05491 Rev. *A
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