CY7C1302CV25 Datasheet, PDF (5/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

PREMILINARY
CY7C1302CV25
Truth Table^{[2, 3, 4, 5, 6, 7]}
Operation
K
Write Cycle:
L-H
Load address on the rising edge of K clock; input write
data on K and K rising edges.
Read Cycle:
L-H
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
NOP: No Operation
L-H
Standby: Clock Stopped
Stopped
Write Cycle Descriptions^[2,8]
RPS
X
L
H
X
WPS
L
X
H
X
DQ
D(A+0)at
K(t) ↑
DQ
D(A+1) at
K(t) ↑
Q(A+0) at Q(A+1) at
C(t+1)↑
C(t+1) ↑
D=X
Q = High-Z
Previous
State
D=X
Q = High-Z
Previous
State
BWS₀ BWS₁
K
L
L
L-H
L
L
–
L
H
L-H
L
H
–
H
L
L-H
H
L
–
H
H
L-H
K
Comments
– During the Data portion of a Write sequence, both bytes (D_[17:0]) are written into the device.
L-H During the Data portion of a Write sequence, both bytes (D_[17:0]) are written into the device.
– During the Data portion of a Write sequence, only the lower byte (D_[8:0]) is written into the
device. D_[17:9] remains unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D_[8:0]) is written into the
device. D_[17:9] remains unaltered.
– During the Data portion of a Write sequence, only the byte (D_[17:9]) is written into the device.
D_[8:0] remains unaltered.
L-H During the Data portion of a Write sequence, only the byte (D_[17:9]) is written into the device.
D_[8:0] remains unaltered.
– No data is written into the device during this portion of a Write operation.
H
H
–
L-H No data is written into the device during this portion of a Write operation.
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS₀, BWS₁ can be altered on different portions of a Write cycle, as long
as the set-up and hold requirements are achieved.
Document #: 38-05491 Rev. *A
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