CY7C1302CV25 Datasheet, PDF (13/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

TAP Controller Block Diagram
PREMILINARY
CY7C1302CV25
0
TDI
Selection
Circuitry
Bypass Register
210
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . 2 1 0
Identification Register
106 . . . . 2 1 0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range ^{[11, 9, 25]}
Parameter
V_OH1
V_OH2
V_OL1
V_OL2
V_IH
V_IL
I_X
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and Output Load Current
Test Conditions
I_OH = −2.0 mA
I_OH = −100 µA
I_OL = 2.0 mA
I_OL = 100 µA
GND ≤ V_I ≤ V_DDQ
Min.
1.7
2.1
1.7
–0.3
–5
Max.
Unit
V
V
0.7
V
0.2
V
V_DD + 0.3
V
0.7
V
5
µA
TAP AC Switching Characteristics Over the Operating Range ^{[26, 27]}
Parameter
Description
Min.
Max.
t_TCYC
t_TF
t_TH
t_TL
Set-up Times
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
100
10
40
40
t_TMSS
TMS Set-up to TCK Clock Rise
10
t_TDIS
TDI Set-up to TCK Clock Rise
10
t_CS
Capture Set-up to TCK Rise
10
Hold Times
t_TMSH
TMS Hold after TCK Clock Rise
10
t_TDIH
TDI Hold after Clock Rise
10
t_CH
Capture Hold after Clock Rise
10
Notes:
25. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
26. T_CS and T_CH refer to the set-up and hold time requirements of latching data from the boundary scan register.
27. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05491 Rev. *A
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